1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a configuration of a memory cell array portion of a static type memory (static random access memory; SRAM) operating statically. More particularly, the present invention relates to a configuration of an SRAM capable of writing and reading data in a stable manner with a reduced current dissipation.
2. Description of the Background Art
One approach of increasing an operating speed of a MOS transistor (insulated gate type field effect transistor) is to reduce the absolute value of a threshold voltage of the transistor. With a smaller absolute value of the threshold voltage, the drain current of the MOS transistor increases, so that it is possible to charge and discharge an internal node at high speed.
When the absolute value of the threshold voltage is made small, however, the source-drain leakage current (sub-threshold current) in an off state increases, leading to an increased current dissipation. Various approaches have been proposed to resolve a problem of such leakage current.
Japanese Patent Laying-Open No. 9-73784 (referred to as patent publication reference 1) describes a semiconductor memory device wherein, in a static type memory cell circuit, a source-substrate (back gate) voltage of a memory cell transistor is changed between the period at the standby and the period of an operation for data accessing. Specifically, during the standby state, the source-substrate voltage of a memory cell MOS transistor is set to a deep reverse bias state and the absolute value of the threshold voltage of the MOS transistor is increased to reduce a leakage current. During the operation, the source and the substrate are kept at the same potential, and the absolute value of the threshold voltage is decreased compared to that at the standby state to achieve a high speed operation. The configuration described in this prior art document aims at increasing the operating speed of the memory while decreasing the current dissipation in a non-operation state (at the standby).
Further, a configuration for speeding up an operation and reducing the current consumption by controlling substrate potentials of a plurality of memory cells individually is described in an article by Kawaguchi et al, titled “Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's”, IEEE 1998 VLSI Circuits Symposium (referred to as non-patent publication reference 1). In the configuration described in this article, in the memory array having memory cells arranged in rows and columns, substrate power supply lines are arranged in the row direction, and the substrate potentials are controlled in units of memory cell rows. Specifically, the substrate potential and the source potential of the memory cell transistors of the memory cell row selected by a row decoder are set to equal potentials to speed up the operation. The substrate potential of the memory cell transistors in a non-selected row is set to a potential at which the source and back gate are set in a reverse bias state to reduce the leakage current in the non-selected memory cells.
Further, as a way of accelerating data writing, a configuration changing substrate potentials of memory cell transistors is disclosed in Japanese Patent Laying-Open No. 11-213673 (referred to as patent publication reference 2). In this reference, the substrate potentials of the transistors of inverter circuits constituting a flip-flop of a static type memory cell are controlled. Specifically, at the beginning of a writing operation, the substrate potentials of the memory cell transistors are so set as to decrease the current driving capabilities of load P channel MOS transistors and drive N channel MOS transistors. In the configuration described in this reference, a substrate potential setting circuit is provided for each memory cell row, and the substrate potentials of the memory cell transistors are adjusted in units of rows.
Layouts for reducing an area of an SRAM cell array are described in Japanese Patent Laying-Open Nos. 10-178110, 2003-60089 and 2001-339071 (referred to as “patent publication references 3, 4 and 5, respectively).
In each of the configurations described in the aforementioned patent publication reference 1 and non-patent publication reference 1, the substrate potential is controlled to be different for an operation of a data accessing to the memory cell and for the standby state (in a non-selected state) to achieve speed up of an operation and reduction of current consumption. In these conventional configurations, however, the absolute values of the threshold voltages of both P and N channel MOS transistors of the memory cell are reduced during the operation to increase the current driving capabilities of the transistors. Thus, although the bit line current-can be discharged at high speed in data reading and the reading operation can be speeded up, for data writing, significant speed-up of writing operation would not be expected so much. In data writing, one and the other bit lines of a bit line pair are strongly driven to an H level and an L level, respectively, by a write driver arranged outside the array, in accordance with data to be written. Data storage nodes of the memory cell are each set to a voltage level in accordance with the write data. In writing of reverse data of the held data, data writing is performed by inverting the H level side node of the storage nodes is inverted to an L level. At this time, when the current driving capability of the PMOS load transistors is large, it is not possible to invert the held data. Thus, it is preferable from the standpoint of high-speed and stable data writing that the current driving capability of the PMOS load transistor is as small as possible compared to that of the NMOS access transistor in a memory cell to which data is to be written. These conventional approaches fail to consider a configuration for writing data at high speed. Consideration is conventionally paid merely to reduction of an absolute value of the threshold voltage of the memory cell transistor during an operation to speed up the operation of the memory cell transistors.
In the above-described patent publication reference 2, the substrate potential setting circuit is arranged for each memory cell row, and substrate potentials of the memory cell transistors are controlled in units of rows. With this configuration, however, data held in the memory cell in a non-selected column may be destructed.
In an SRAM cell, stability of data retention is given quantitatively by characteristic curves obtained by inverting and superimposing input and output transfer characteristic curves of an inverter. A larger area of the region delimited by the two characteristic curves ensures more stable data retention. The area of this region is called a static noise margin (SNM). The static noise margin depends on an input logic threshold of the inverter, and thus, depends on current driving capabilities and threshold voltages of the MOS transistors constituting an SRAM cell. For example, in an SRAM cell of a full CMOS configuration, when a ratio between the current driving capability of an accessing N channel MOS transistor and the current driving capability of a driving N channel MOS transistor becomes small, a potential of an L level storage node is likely to rise upon connection to a bit line. The static noise margin decreases, and the stability of data retention is reduced. In other words, data held in the memory cell is destructed, thereby causing a malfunction. This ratio of the current driving capabilities is generally called a 0 ratio, which is normally set to more than 1.5 to secure the static noise margin. In other words, it is necessary to set the current driving capability of the drive transistor higher than that of the access transistor.
In an SRAM, it is important to secure the static noise margin to ensure stability of data retention. If the substrate potentials are controlled to reduce the current driving capability of the drive transistor at the start of data writing operation, as in the configuration of the above-described patent publication reference 2, the static noise margin is reduced and is advantageous for data writing. In this approach, storage nodes of the memory cells in a selected row and in non-selected columns are also connected to the corresponding bit lines. Thus, when the substrate potentials are controlled to reduce the current driving capabilities of the drive transistors of the memory cells in units of memory cell rows, the static noise margin would decrease also in the memory cells in the selected row and in the non-selected columns. This may destruct the memory cell data in the non-selected columns and hence cause a malfunction.
In each of the conventional techniques, although reduction of current consumption at the standby is considered, reduction of active current due to charge/discharge of bit lines during an operation is given no consideration.
Further, the above-described patent publication references 3–5 each consider only the layout of the memory cells, and give no consideration on circuit characteristics such as reduction of current consumption.